The embodiments described below involve the developing and ever-expanding field of computer systems and microprocessors. Modern microprocessors now include one or more pipelines with numerous stages so that different instructions may be at different stages at the same time of operation. Moreover, some microprocessors include more than one pipeline in this manner and, therefore, can perform more than one instruction execution at a time. Naturally, the ability to execute more than one instruction at a time provides vast increases in processor speed and, therefore, is highly desirable. Nevertheless, these advanced techniques give rise to countless design complexities.
Certain design complexities arise from considerations of branch instructions, that is, those instructions which direct program control away from the otherwise sequential operation established by sequentially oriented software. Various techniques are now in the art to handle certain branch complexities, such as those which predict the likelihood that the condition of a branch will or will not be satisfied (sometimes referred to as "taken" or "not taken", respectively). These processes are particularly useful in a superscalar microprocessor. For example, consider the instance where a branch instruction arranged first in a sequence is followed at some point thereafter by some later-occurring instruction which, if executed, would cause some result. If a prediction technique accurately states that the branch will be satisfied (i.e., branch taken), then it may well be worthwhile not to concurrently execute the later-occurring instruction. On the other hand, if the prediction technique accurately states that the branch condition will not be satisfied (i.e., branch not taken), then it may well be appropriate and advantageous to concurrently execute the later-occurring instruction.
While branch prediction techniques are, in general, beneficial in certain instances, mis-predictions of branch execution can be very costly in terms of microprocessor efficiency. For example, as the pipelines of modern superscalar machines get deeper (i.e., hold more instructions at varying stages at once), and as such machines also become superpipelined (i.e., capable of more concurrent executions), a mispredicted branch may heavily penalize performance by requiring a pipeline or pipelines to be emptied and subsequently re-filled with instructions from the correct target address. In this instance, numerous cycles are required to reset the pipeline(s) to an operational state and, thus, valuable processor cycle time is lost. While modern branch target buffer technology reduces the flush/refill penalty rate by often correctly predicting program flow past branches, the branch misprediction penalty that remains is one of the more serious impediments to realizing even higher processor performance.
In view of the above, there arises a need to address the drawbacks of the effects of mispredicted branches in a pipelined microprocessor.